1. Field of the Invention
The present invention relates to Rambus DRAM and, more particularly, to Rambus DRAM capable of reducing power consumption and layout area by enabling data read/write control signal of accessed memory bank only, in a top memory bank and a bottom memory bank.
2. Description of Related Art
FIG. 1 is a block diagram of conventional Rambus DRAM. Referring to FIG. 1, the Rambus DRAM comprises a top memory bank block 1 and a bottom memory bank block 4 comprising a plurality of memory banks, respectively and data read/write control signal generation block 7 for generating data read/write control signal to the top and bottom memory bank blocks 1,4.
The top memory bank block 1 includes a DQA memory bank block 2 comprising 9 unit memory banks S1-S9 controlled by data signal received through data input/output pin DQA and a DQB memory bank block 3 comprising 9 unit memory banks S1-S9 controlled by data signal received through DQB pin.
The bottom memory bank block 4 includes a DQA memory bank block 5 comprising 9 unit memory banks S1-S9 controlled by data signal received through DQA pin and a DQB memory bank block 6 comprising 9 unit memory banks S1-S9 controlled by data signal received through DQB pin.
The data read/write control signal generation block 7 of FIG. 1 generates data write control signal writeD0123, write D4567 to 36 unit memory banks of top and bottom memory bank blocks 1, 4 in data write operation to enable them at the same time. And, in data read operation, the data read/write control signal generation block 7 generates data read control signal loadRDpipe to 36 unit memory banks of top and bottom memory bank blocks 1, 4 to enable all of them at the same time. As a result, the conventional Rambus DRAM has a problem of excessive power consumption.
FIG. 2A is a data write transmission circuit diagram controlled by data write control signal writeD0123 of each unit memory bank in FIG. 1, comprising 4 latch units 11 and 1 control unit 12.
The 4 latch units 11 latch data received through input pad (not shown) and then, transmits the data to memory cell (not shown) and the control unit 12 receives write data control signal writeD0123 and then, generates signal controlling operation of the 4 latch units 11.
FIG. 2B is a data write transmission circuit diagram controlled by data write control signal writeD4567 of each memory bank in FIG. 1, comprising 8 latch units 13 and 1 control unit 14.
The 8 latch units 13 latch data received through pad (not shown) and then, transmits the data to memory cell (not shown) and the control unit 14 receives data write control signal writeD4567 and then, generates signal controlling operation of the 8 latch units 13.
FIG. 3A is a data read transmission circuit diagram controlled by data read control signal loadRDpip of each memory bank in FIG. 1, comprising 8 latch units 15 and 1 control unit 16.
The 8 latch units 15 transmit data received from memory cell (not shown) to pad (not shown) and the control unit 16 receives data read control signal loadRDpipe to generate signal controlling operation of the 8 latch units 15.
FIG. 3B is a data read transmission circuit diagram controlled by data read control signal drainRDpipe of each memory bank in FIG. 1, comprising 8 latch units 17 and 1 control unit 16.
The 8 latch unit 17 transmits data received from memory cell (not shown) to pad (not shown) and the control unit 16 receives data read control signal drainRDpipe to generate signal controlling operation of the 8 latch units 17.
FIG. 4A is a waveform of conventional data write control signal comprising an external clock rclk, a top memory enable clock sclk_en_top, a bottom memory enable clock sclk_en_bot, a pre data write signal writeD0123_pre, a pre data write signal writeD4567_pre, a data write control signal writeD0123 and a data write control signal writeD4567.
In the data write control signal writeD0123 and the data write control signal writeD4567, a first clock is a signal for operating the top memory bank and a second clock is a signal for operating the bottom memory bank. The top and the bottom memory banks are simultaneously operated by the data write control signal writeD0123 and the data write control signal writeD4567 in the section overlapped by the top memory enable clock sclk_en_top and the bottom memory enable clock sclk_en_bot.
FIG. 4B is a circuit diagram of conventional data write control signal generation circuit, showing a data write control signal writeD0123 generation block 21 and a data write control signal writeD4567 generation block 23.
The data write control signal writeD0123 generation block 21 comprises a first pre data write generation block 22 and two inverters 23,24 connected in a series. The first pre data write generation block 22 generates a pre data write signal writeD0123_pre and two inverters 23,24 receives the pre data write signal writeD0123_pre to generate a data write control signal writeD0123.
The data write control signal writeD4567 generation block 25 comprises a second pre data write generation block 26 and two inverters 27,28 connected in a series. The second pre data write generation block 26 generates a pre data write signal writeD4567_pre and the two inverters 27,28 receives the pre data write signal writeD4567_pre to generate a data write control signal writeD4567.
FIG. 5A is a waveform of conventional data read control signal loadRDpipe comprising an external clock rclk, a pre data read signal loadRDpipe_pre and a data read control signal loadRDpipe. The data read control signal loadRDpipe includes a clock signal for accessing top and bottom memory banks in the sections 8-c of external clock rclk.
FIG. 5B is a diagram of conventional data read control signal loadRDpipe generation circuit comprising a pre data read generation block 31 and two inverters 32,33 connected in a series.
The pre data read generation block 31 generates a pre data read signal loadRDpipe_pre and the two inverters 32,33 receives the pre data write signal loadRDpipe_pre to generate a data read control signal loadRDpipe.
FIG. 5C is a waveform of conventional data read control signal drainRDpipe comprising an external clock rclk, a domain control block signal load_out, a top bank selection signal top_bank_sel, a bottom bank selection signal bot_bank_sel, a bottom data read clock signal load_outpipe_bot, a top data read clock signal load_outpipe_top, a bottom data read control signal drainRDpipe_bot and a top data read control signal drainRDpipe_top.
The bottom data read control signal drainRDpipe_bot is generated by the bottom data read clock signal load_outpipe_bot and the top data read control signal drainRDpipe_top is generated by the top data read clock signal load_outpipe_top.
The bottom data read clock signal load_outpipe_bot and the top data read clock signal load_outpipe_top are generated by the domain control block signal load_out.
FIG. 5D is a diagram of conventional data read control signal drainRDpipe generation circuit comprising a top data read control signal drainRDpipe_top generation circuit unit 40 including a domain control unit 41, two inverters 42,43 and a top data read control signal generation block 44, and a bottom data read control signal drainRDpipe_bot generation circuit unit 50 including a domain control unit 51, two inverters 52,53 and a top data read control signal generation block 54.
The top data read control signal drainRDpipe_top generation circuit unit 40 comprises a domain control unit 41 for receiving a domain control block signal load_out by a top bank selection signal top_bank_sel and outputting a pre data read clock signal load_outpipe_pre, two inverters 42, 43 connected in a series for receiving the output signal load_outpipe_pre of the domain control unit 41 and outputting a top data read clock signal load_outpipe_top and a top data read control signal generation block 44 for receiving an output signal load_outpipe_top of the inverter 43 and outputting a top data read control signal drainRDpipe_top.
The bottom data read control signal drainRDpipe_bot generation circuit unit 50 comprises a domain control unit 51 for receiving a domain control block signal load_out by a bottom bank selection signal bot_bank_sel and outputting a pre data read clock signal load_outpipe_pre, two inverters 52,53 connected in a series for receiving an output signal load_outpipe_pre of the domain control unit 51 and outputting a bottom data read clock signal load_outpipi_bot and a bottom data read control signal generation block 54 for receiving an output signal load_outpipe_bot of the inverter 53 and outputting a bottom data read control signal drainRDpipe_bot.
However, the conventional Rambus DRAM has a problem of excessive power consumption since data write control signals writeD0123, writeD4567 are toggled, thereby simultaneously operating data write path of top and bottom memory banks in writing data to the top memory bank and data read control signal loadRDpipe is toggled, thereby simultaneously operating data read path of top and bottom memory banks in reading data of the top memory bank block.
And, the conventional data read control signal drainRDpipe path is operated by dividing top and bottom memory banks. In this case, the data read control signal drainRDpipe is generated by each block path and the domain control unit has a complicated circuit structure, thereby increasing power consumption and layout area.